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6 BIT 420 CHANNEL RSDS TFT-LCD SOURCE DRIVER
PREMILINARY VER 1.0
S6C0679
S6C0679
6 BIT 420 CHANNEL RSDS TFT-LCD SOURCE DRIVER
January.2000. Ver. 0.0
Prepared by:
Akira Kang
akira211@samsung.co.kr
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S6C0679
PREMILINARY VER 1.0
6 BIT 420 CHANNEL RSDS TFT-LCD SOURCE DRIVER
S6C0679 Specification Revision History Version 0.0 Original Content Date Jan.2000.
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6 BIT 420 CHANNEL RSDS TFT-LCD SOURCE DRIVER
PREMILINARY VER 1.0
S6C0679
CONTENTS
INTRODUCTION ................................................................................................................................................. 4 FEATURES ......................................................................................................................................................... 4 BLOCK DIAGRAM .............................................................................................................................................. 5 PIN ASSINGMENTS............................................................................................................................................ 6 PIN DESCRIPTIONS ........................................................................................................................................... 7 OPERATION DESCRIPTION............................................................................................................................... 8 RSDS RECEIVER AND DEMUX ...................................................................................................................... 8 RSDS DATA BUS INTERFACE CONTROL ...................................................................................................... 8 DISPLAY DATA TRANSFER ............................................................................................................................ 8 EXTENSION OF OUTPUT ............................................................................................................................... 8 RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE .................................................. 8 ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 15 RECOMMENDED OPERATION CONDITIONS.................................................................................................. 15 DC CHARACTERISTICS................................................................................................................................... 16 RSDS CHARACTERISTICS .............................................................................................................................. 17 AC CHARACTERISTICS................................................................................................................................... 18 WAVEFORMS ................................................................................................................................................... 19 RSDS DATA TIMING DIAGRAM ....................................................................................................................... 20
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S6C0679
PREMILINARY VER 1.0
6 BIT 420 CHANNEL RSDS TFT-LCD SOURCE DRIVER
INTRODUCTION
The S6C0679 is a Source Driver suitable for Reduced Swing Differential Signaling (RSDS) digital interface. It converts 18-bit digital data into the analog voltage for 420 channels, charging each sub-pixel to the correct gray level corresponding to the digital value. The RSDS path to the panel timing controller contributes toward lowering radiated EMI, reducing system power consumption and eliminates one of the two pixel busses used in typical SXGA+ TFT LCD panels. This single 9-bit differential bus conveys the 18-bit color data for SXGA+ panels.
FEATURES
* * * * * * * * * * * * * TFT active matrix LCD source driver LSI 64 G/S is possible through 10 (5 by 2) external power supply and D/A converter Both dot inversion display and N-line inversion display are possible Compatible with gamma-correction Logic supply voltage: 2.7 to 3.6 V LCD driver supply voltage: 7.0 to 10.5 V Output dynamic range: 6.8 to 10.3 Vp-p Maximum operating frequency: fmax = 65 MHz (internal data transmission rate at 2.7 V operation) Output: 420 outputs Reduced Swing Differential Signaling (RSDS) digital interface for low power consumption and low EMI. Minimum RSDS input swing level (CLKN, CLKP, DATAN, DATAP): 100mV Data bus interface control pin (DATPOL) TCP or COF available
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6 BIT 420 CHANNEL RSDS TFT-LCD SOURCE DRIVER
PREMILINARY VER 1.0
S6C0679
BLOCK DIAGRAM
Y418
Y419 6
POL
Output Buffer
R-DAC
VGMA1 to VGMA10
6
6
6
6
6
CLK1
Data Latches
D00P D00N D01P D01N D22P D22N
6
RSDS Receiver
Data Register
6 6 6
6 6
140 bit Shift Register
DATPOL
CLKP CLKN
DIO1
SHL
DIO2
RPI1
RPO1
Line Repair AMP
RPI2 RPO2
Figure 1. S6C0679 Block Diagram
Y420
Y1
Y2
Y3
5
S6C0679
PREMILINARY VER 1.0
6 BIT 420 CHANNEL RSDS TFT-LCD SOURCE DRIVER
PIN ASSINGMENTS
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12
Y408 Y409 Y410 Y411 Y412 Y413 Y414 Y415 Y416 Y417 Y418 Y419 Y420
RPI1 RPO1 DIO1 D00N D00P D01N D01P D02N D02P DATPOL POL CLK1 CLKN CLKP VSS1 VGMA1 VGMA2 VGMA3 VGMA4 VGMA5 VSS2 VDD2 VGMA6 VGMA7 VGMA8 VGMA9 VGMA10 SHL VDD1 D10N D10P D11N D11P D12N D12P D20N D20P D21N D21P D22N D22P DIO2 RPO2 RPI2
Output 420
S6C0679
Input 44
Figure 2. S6C0679 Pin Assignments
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6 BIT 420 CHANNEL RSDS TFT-LCD SOURCE DRIVER
PREMILINARY VER 1.0
S6C0679
PIN DESCRIPTIONS
Symbol VDD1 VDD2 VSS1 VSS2 Y1 to Y420 D0P<0:2> D0N<0:2> D1P<0:2> D1N<0:2> D2P<0:2> D2N<0:2> SHL Pin Name Logic power supply Driver power supply Logic ground Driver ground Driver outputs 2.7 to 3.6 V 7.0 to 10.5 V Ground (0 V) Ground (0 V) The D/A converted 64 gray-scale analog voltage is output. Total data lines consist of 18 data bus. (6-bit digital, 3 colors (R, G, B) and 2 differential input pairs) The 3 - bit differential input pairs generate the internal 6 - bit data through the comparison between DxxP and DxxN. This pin controls the direction of shift register in cascade connection. When SHL = H: DIO1 input, Y1 Y420, DIO2 output When SHL = L: DIO2 input, Y420 Y1, DIO1 output SHL = H: Used as the start pulse input pin. SHL = L: Used as the start pulse output pin. SHL = H: Used as the start pulse output pin. SHL = L: Used as the start pulse input pin. DATPOL = L: No inversion DATPOL = H: Data polarity inversion (HL) POL = H: The reference voltage for odd number outputs are VGMA1 to VGMA5 and those for even number outputs are VGMA6 to VGMA10. POL = L: The reference voltage for odd number outputs are VGMA6 to VGMA10 and those for even number outputs are VGMA1 to VGMA5. The RSDS clock input pairs generate the internal shift clock, CLK2, through the comparison between CLKP and CLKN. S6C0679 clears 140 shift registers at the rising edge of CLK1 and outputs the analog data to the each channel at the falling edge. Input the gamma corrected power supplies from external source. VDD2 > VGMA1 > VGMA2 > ...... > VGMA9 > VGMA10 > VSS2 Keep power supplies unchanged during the gray-scale voltage output. The Structure of the line-repair amp is the same as that of the analog output. RPI1 (RPI2) impedance changed RPO1 (RPO2) TEST = L: Normal operation mode TEST = H: Test mode (OP AMP CUT-OFF, Rpd = 15 k) Description
RSDS data input
Shift direction control input Start pulse input / output Start pulse input / output Data inversion input
DIO1 DIO2 DATPOL
POL
Polarity input
CLKP CLKN CLK1 VGMA1 to VGMA10 RPI1, RPO1 RPI2, RPO2 TEST
RSDS shift clock input Latch input Gamma corrected power supplies Line-repair AMP input / output Test input
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S6C0679
PREMILINARY VER 1.0
6 BIT 420 CHANNEL RSDS TFT-LCD SOURCE DRIVER
OPERATION DESCRIPTION
RSDS RECEIVER AND DEMUX The S6C0679 adapts the RSDS interface for EMI solution. The internal RSDS receiver block operates the comparison between the transmitted differential input pair data. The input data lines from the timing controller to the RSDS receiver consist of 6-bit digital, 3 colors, 1 port, 2 differential pairs (DxxP / DxxN). The input common mode voltage range at the RSDS receiver is 1.2 V. The differential data and clock signals from the panel timing controller arrive at the S6C0679 as multiplexed, even and odd data fields. (i.e., the data is 2:1 multiplexed). The nominal peak to peak swing of this data is 200 mV across a termination resistor.
RSDS DATA BUS INTERFACE CONTROL DATPOL controls the internal data inversion. When DATPOL = " H" , the internal data is inverted. The inverted data is the same that the RSDS receiver operates the comparison between the cross-transmitted differential input pair data. Using the data inversion input pin, DATPOL, the RSDS data bus interface can be changed.
DISPLAY DATA TRANSFER When DIO1 (or DIO2) pulse is loaded into the internal latch on the falling edge of CLKP, DIO1 (or DIO2) pulse enables the operation of data transfer, so display data is valid on the 2nd falling edge of CLKP. Once all the data of 420 channels is loaded into internal latch, it goes into stand-by state automatically, and any new data is not accepted even though CLKP is provided until next DIO1 (or DIO2) input. When next DIO1 (or DIO2) is provided, new display data is valid on the 2nd falling edge of CLKP after the rising edge of DIO1 (or DIO2).
EXTENSION OF OUTPUT Output pin can be adjusted to an extended screen by cascade connection. When SHL = "L", Connect DIO1 pin of the previous stage to the DIO2 pin of the next stage and all the input pins except DIO1 and DIO2 are connected together in each device. When SHL = "H", Connect DIO2 pin of the previous stage to the DIO1 pin of the next stage and all the input pins except DIO2 and DIO1 are connected together in each device.
RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE The LCD drive output voltages are determined by the input data and 10 (5 by 2) gamma corrected power supplies (VGMA1 to VGMA10). Besides, to be able to deal with dot line inversion when mounted on a singleside, gradation voltages with different polarity can be output to the odd number output pins and the even number output pins. Among 5 by 2 gamma corrected voltages, input gray scale voltages of the same polarity with respect to the common voltage, for the respective 5 gamma corrected voltages of VGMA1 to VGMA5 and VGMA6 to VGMA10.
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6 BIT 420 CHANNEL RSDS TFT-LCD SOURCE DRIVER
PREMILINARY VER 1.0
S6C0679
VDD2 VGMA1
VGMA2 VGMA3 VGMA4 VGMA5 VGMA6 VGMA7 VGMA8 VGMA9
VCOM
VGMA10 VSS2 00H 08H 10H 18H 20H 28H 30H 38H 3FH Input data
Figure 3. Gamma Correction Curve
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S6C0679
PREMILINARY VER 1.0
6 BIT 420 CHANNEL RSDS TFT-LCD SOURCE DRIVER
Table 1. Resistor Strings (R0 to R62, unit: ) Name R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Value 500 500 500 500 500 500 500 500 500 500 500 500 450 450 400 370 Name R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 Value 330 330 330 320 300 280 270 260 250 240 230 220 210 200 190 180 Name R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 Value 175 175 170 170 165 165 165 165 170 170 170 175 175 175 180 200 Name R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 Value 210 220 230 240 250 260 270 290 300 310 320 340 340 340 340
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6 BIT 420 CHANNEL RSDS TFT-LCD SOURCE DRIVER
PREMILINARY VER 1.0
S6C0679
Table 2. Relationship between Input Data and Output Voltage Value Input Data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH DX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 G/S VH0 VH1 VH2 VH3 VH4 VH5 VH6 VH7 VH8 VH9 VH10 VH11 VH12 VH13 VH14 VH15 VH16 VH17 VH18 VH19 VH20 VH21 VH22 VH23 VH24 VH25 VH26 VH27 VH28 VH29 VH30 VH31 Output Voltage VGMA1 VGMA1+(VGMA2 - VGMA1) x 500/7670 VGMA1+(VGMA2-VGMA1) x 1000/7670 VGMA1+(VGMA2-VGMA1) x 1500/7670 VGMA1+(VGMA2-VGMA1) x 2000/7670 VGMA1+(VGMA2-VGMA1) x 2500/7670 VGMA1+(VGMA2-VGMA1) x 3000/7670 VGMA1+(VGMA2-VGMA1) x 3500/7670 VGMA1+(VGMA2-VGMA1) x 4000/7670 VGMA1+(VGMA2-VGMA1) x 4500/7670 VGMA1+(VGMA2-VGMA1) x 5000/7670 VGMA1+(VGMA2-VGMA1) x 5500/7670 VGMA1+(VGMA2-VGMA1) x 6000/7670 VGMA1+(VGMA2-VGMA1) x 6450/7670 VGMA1+(VGMA2-VGMA1) x 6900/7670 VGMA1+(VGMA2-VGMA1) x 7300/7670 VGMA2 VGMA2+(VGMA3-VGMA2) x 330/4140 VGMA2+(VGMA3-VGMA2) x 660/4140 VGMA2+(VGMA3-VGMA2) x 990/4140 VGMA2+(VGMA3-VGMA2) x 1310/4140 VGMA2+(VGMA3-VGMA2) x 1610/4140 VGMA2+(VGMA3-VGMA2) x 1890/4140 VGMA2+(VGMA3-VGMA2) x 2160/4140 VGMA2+(VGMA3-VGMA2) x 2420/4140 VGMA2+(VGMA3-VGMA2) x 2670/4140 VGMA2+(VGMA3-VGMA2) x 2910/4140 VGMA2+(VGMA3-VGMA2) x 3140/4140 VGMA2+(VGMA3-VGMA2) x 3360/4140 VGMA2+(VGMA3-VGMA2) x 3570/4140 VGMA2+(VGMA3-VGMA2) x 3770/4140 VGMA2+(VGMA3-VGMA2) x 3960/4140
NOTE: VDD2 > VGMA1 > VGMA2 > VGMA3 > VGMA4 > VGMA5
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S6C0679
PREMILINARY VER 1.0
6 BIT 420 CHANNEL RSDS TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value (Continued) Input Data 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH DX5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 G/S VH32 VH33 VH34 VH35 VH36 VH37 VH38 VH39 VH40 VH41 VH42 VH43 VH44 VH45 VH46 VH47 VH48 VH49 VH50 VH51 VH52 VH53 VH54 VH55 VH56 VH57 VH58 VH59 VH60 VH61 VH62 VH63 Output Voltage VGMA3 VGMA3+(VGMA4-VGMA3) x 175/2765 VGMA3+(VGMA4-VGMA3) x 350/2765 VGMA3+(VGMA4-VGMA3) x 520/2765 VGMA3+(VGMA4-VGMA3) x 690/2765 VGMA3+(VGMA4-VGMA3) x 855/2765 VGMA3+(VGMA4-VGMA3) x 1020/2765 VGMA3+(VGMA4-VGMA3) x 1185/2765 VGMA3+(VGMA4-VGMA3) x 1350/2765 VGMA3+(VGMA4-VGMA3) x 1520/2765 VGMA3+(VGMA4-VGMA3) x 1690/2765 VGMA3+(VGMA4-VGMA3) x 1860/2765 VGMA3+(VGMA4-VGMA3) x 2035/2765 VGMA3+(VGMA4-VGMA3) x 2210/2765 VGMA3+(VGMA4-VGMA3) x 2385/2765 VGMA3+(VGMA4-VGMA3) x 2565/2765 VGMA4 VGMA4+(VGMA5-VGMA4) x 210/4260 VGMA4+(VGMA5-VGMA4) x 430/4260 VGMA4+(VGMA5-VGMA4) x 660/4260 VGMA4+(VGMA5-VGMA4) x 900/4260 VGMA4+(VGMA5-VGMA4) x 1150/4260 VGMA4+(VGMA5-VGMA4) x 1410/4260 VGMA4+(VGMA5-VGMA4) x 1680/4260 VGMA4+(VGMA5-VGMA4) x 1970/4260 VGMA4+(VGMA5-VGMA4) x 2270/4260 VGMA4+(VGMA5-VGMA4) x 2580/4260 VGMA4+(VGMA5-VGMA4) x 2900/4260 VGMA4+(VGMA5-VGMA4) x 3240/4260 VGMA4+(VGMA5-VGMA4) x 3580/4260 VGMA4+(VGMA5-VGMA4) x 3920/4260 VGMA5
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6 BIT 420 CHANNEL RSDS TFT-LCD SOURCE DRIVER
PREMILINARY VER 1.0
S6C0679
Table 2. Relationship between Input Data and Output Voltage Value (Continued) Input Data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH DX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 G/S VL0 VL1 VL2 VL3 VL4 VL5 VL6 VL7 VL8 VL9 VL10 VL11 VL12 VL13 VL14 VL15 VL16 VL17 VL18 VL19 VL20 VL21 VL22 VL23 VL24 VL25 VL26 VL27 VL28 VL29 VL30 VL31 Output Voltage VGMA10 VGMA10+(VGMA9-VGMA10) x 500/7670 VGMA10+(VGMA9-VGMA10) x 1000/7670 VGMA10+(VGMA9-VGMA10) x 1500/7670 VGMA10+(VGMA9-VGMA10) x 2000/7670 VGMA10+(VGMA9-VGMA10) x 2500/7670 VGMA10+(VGMA9-VGMA10) x 3000/7670 VGMA10+(VGMA9-VGMA10) x 3500/7670 VGMA10+(VGMA9-VGMA10) x 4000/7670 VGMA10+(VGMA9-VGMA10) x 4500/7670 VGMA10+(VGMA9-VGMA10) x 5000/7670 VGMA10+(VGMA9-VGMA10) x 5500/7670 VGMA10+(VGMA9-VGMA10) x 6000/7670 VGMA10+(VGMA9-VGMA10) x 6450/7670 VGMA10+(VGMA9-VGMA10) x 6900/7670 VGMA10+(VGMA9-VGMA10) x 7300/7670 VGMA9 VGMA9+(VGMA8-VGMA9) x 330/4140 VGMA9+(VGMA8-VGMA9) x 660/4140 VGMA9+(VGMA8-VGMA9) x 990/4140 VGMA9+(VGMA8-VGMA9) x 1310/4140 VGMA9+(VGMA8-VGMA9) x 1610/4140 VGMA9+(VGMA8-VGMA9) x 1890/4140 VGMA9+(VGMA8-VGMA9) x 2160/4140 VGMA9+(VGMA8-VGMA9) x 2420/4140 VGMA9+(VGMA8-VGMA9) x 2670/4140 VGMA9+(VGMA8-VGMA9) x 2910/4140 VGMA9+(VGMA8-VGMA9) x 3140/4140 VGMA9+(VGMA8-VGMA9) x 3360/4140 VGMA9+(VGMA8-VGMA9) x 3570/4140 VGMA9+(VGMA8-VGMA9) x 3770/4140 VGMA9+(VGMA8-VGMA9) x 3960/4140
NOTE: VGMA6 > VGMA7 > VGMA8 > VGMA9 > VGMA10 > VSS2
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S6C0679
PREMILINARY VER 1.0
6 BIT 420 CHANNEL RSDS TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value (Continued) Input Data 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH DX5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 G/S VL32 VL33 VL34 VL35 VL36 VL37 VL38 VL39 VL40 VL41 VL42 VL43 VL44 VL45 VL46 VL47 VL48 VL49 VL50 VL51 VL52 VL53 VL54 VL55 VL56 VL57 VL58 VL59 VL60 VL61 VL62 VL63 Output Voltage VGMA8 VGMA8+(VGMA7-VGMA8) x 175/2765 VGMA8+(VGMA7-VGMA8) x 350/2765 VGMA8+(VGMA7-VGMA8) x 520/2765 VGMA8+(VGMA7-VGMA8) x 690/2765 VGMA8+(VGMA7-VGMA8) x 855/2765 VGMA8+(VGMA7-VGMA8) x 1020/2765 VGMA8+(VGMA7-VGMA8) x 1185/2765 VGMA8+(VGMA7-VGMA8) x 1350/2765 VGMA8+(VGMA7-VGMA8) x 1520/2765 VGMA8+(VGMA7-VGMA8) x 1690/2765 VGMA8+(VGMA7-VGMA8) x 1860/2765 VGMA8+(VGMA7-VGMA8) x 2035/2765 VGMA8+(VGMA7-VGMA8) x 2210/2765 VGMA8+(VGMA7-VGMA8) x 2385/2765 VGMA8+(VGMA7-VGMA8) x 2565/2765 VGMA7 VGMA7+(VGMA6-VGMA7) x 210/4260 VGMA7+(VGMA6-VGMA7) x 430/4260 VGMA7+(VGMA6-VGMA7) x 660/4260 VGMA7+(VGMA6-VGMA7) x 900/4260 VGMA7+(VGMA6-VGMA7) x 1150/4260 VGMA7+(VGMA6-VGMA7) x 1410/4260 VGMA7+(VGMA6-VGMA7) x 1680/4260 VGMA7+(VGMA6-VGMA7) x 1970/4260 VGMA7+(VGMA6-VGMA7) x 2270/4260 VGMA7+(VGMA6-VGMA7) x 2580/4260 VGMA7+(VGMA6-VGMA7) x 2900/4260 VGMA7+(VGMA6-VGMA7) x 3240/4260 VGMA7+(VGMA6-VGMA7) x 3580/4260 VGMA7+(VGMA6-VGMA7) x 3920/4260 VGMA6
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6 BIT 420 CHANNEL RSDS TFT-LCD SOURCE DRIVER
PREMILINARY VER 1.0
S6C0679
ABSOLUTE MAXIMUM RATINGS
Table 3. Absolute Maximum Ratings (VSS1 = VSS2 = 0 V) Parameter Logic supply voltage Driver supply voltage Input voltage Symbol VDD1 VDD2 VGMA1 to 10 RPI1, RPI2 Others DIO1, DIO2 Output voltage Operating power dissipation Operation temperature Storage temperature Y1 to Y420 RPO1, RPO2 Pd Top Tstg CAUTIONS: If LSIs are stressed beyond those listed above "absolute maximum ratings" , they may be permanently destroyed. These are stress ratings only, and functional operation of the device at these or any other condition beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Turn on power order: VDD1 control signal input VDD2 VGMA1 to VGMA10 Turn off power order: VGMA1 to VGMA10 VDD2 control signal input VDD1 Ratings -0.3 to 5.0 -0.3 to 12.0 -0.3 to VDD2 + 0.3 -0.3 to VDD2 + 0.3 -0.3 to VDD1 + 0.3 -0.3 to VDD1 + 0.3 -0.3 to VDD2 + 0.3 -0.3 to VDD2 + 0.3 150 -20 to 75 -55 to 125 mW C C V V Unit V V
RECOMMENDED OPERATION CONDITIONS
Table 4. Recommended Operation Conditions (Ta = - 20 to 70 C, VSS1 = VSS2 = 0 V) Parameter Logic supply voltage Driver supply voltage Gamma corrected voltage Driver part output voltage Maximum clock frequency Output load capacitance fmax Symbol VDD1 VDD2 VGMA1 to VGMA5 VGMA6 to VGMA10 Vyo VDD1 = 2.7V CL Min. 2.7 7.0 0.5VDD2 + 0.1 + 0.1 Typ. 3.0 Max. 3.6 10.5 VDD2 - 0.1 0.5VDD2 VDD2 - 0.1 65 150 Unit V V V V V MHz pF / PIN
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S6C0679
PREMILINARY VER 1.0
6 BIT 420 CHANNEL RSDS TFT-LCD SOURCE DRIVER
DC CHARACTERISTICS
Table 5 . DC Characteristics (Ta = -20 to 75 C, VDD1 = 2.7 to 3.6 V, VDD2 = 7.0 to 10.5 V, VSS1 = VSS2 = 0) Parameter High level input voltage Low level input voltage Input leakage current Repair input leak current High level output voltage Low level output voltage Resistance between gamma voltage Symbol VIH VIL IL1 IL2 VOH VOL R0 to R62 IVOH1 Driver output current IVOL1 IVOH2 IVOL2 DVO dVrms(3) VYO IDD1 RPI1(RPI2) DIO1(DIO2), IO = - 1.0 mA DIO1(DIO2), IO = + 1.0 mA Refer to Table 1. Resistor Strings VDD2 = 8.0 V, Vx(1) = 4.0 V, Vyo(2) = 7.0 V VDD2 = 8.0 V, Vx(1) = 4.0 V, Vyo(2) = 1.0 V VDD2 = 8.0 V, Vx(1) = 4.0 V, Vyo(2) = 7.0 V Vx(1) = VDD2 = 8.0 V, 4.0 V, Vyo(2) = 1.0 V SHL, CLK1, POL, DIO1 (DIO2) Condition Min. 0.7VDD1 0 -1 -1 VDD1 - 0.5 Rn x 0.7 0.4 1.0 VSS2 + 0.1 - 0.8 0.8 -2.0 2.0 10 5 6.0 Typ. Max. VDD1 0.3VDD1 1 1 0.5 Rn x 1.3 - 0.4 mA -1.0 25 15 VDD2 - 0.1 8.0 mV V Unit V A V
Line-repair Driver output current Output voltage deviation Output swing voltage difference deviation Output voltage range Logic part dynamic current
Input data: 00H to 3FH Input data: 00H to 3FH Input data: 00H to 3FH VDD1 = 3.0 V (4) VDD1 = 3.0 V, VDD2 = 9.0 V, VGMA1 = 8.5 V, VGMA5 = 5.0 V, VGMA6 = 4.0 V, VGMA10 = 0.5 V (4) (5)
Driver part dynamic current
mA 8.0 12.0
IDD2
NOTES: 1. Vx is the voltage applied to analog output pins Y1 to Y420. 2. Vyo is the output voltage of analog output pins Y1 to Y420. 3. dVrms = max. deviation of (VHx-VLx) VHx; the x gray level positive polarity driver output voltage VLx; the x gray level negative polarity driver output voltage 4. CLK1 period = 20 s at fCLK2 = 33 MHz, data pattern = 1010......, (checkerboard pattern), Ta = 25 C 5. Yout load condition (refer to Figure 4. Yout Load Condition) applied.
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6 BIT 420 CHANNEL RSDS TFT-LCD SOURCE DRIVER
PREMILINARY VER 1.0
S6C0679
RSDS CHARACTERISTICS
Table 6 . RSDS Characteristics (Ta = - 20 to 75 C, VDD1 = 2.7 to 3.6 V, VDD2 = 7.0 to 10.5 V, VSS1 = VSS2 = 0) Symbol Condition Min. Typ. Max. Unit VIHRSDS VIHRSDS VCMRSDS IDL VCMRSDS = + 1.2 V (1) VCMRSDS = + 1.2 V
(1)
Parameter RSDS high input voltage RSDS low input voltage RSDS common mode input voltage range RSDS input leakage current
100
200 - 200 - 100 VDD1 - 1.5 10
mV V A
VDIFFRSDS = + 200 mV (2) DxxP, DxxN, CLKP, CLKN
VSS1 + 0.1 - 10
-
NOTES: 1. VCMRSDS = (VCLKP + VCLKN) / 2 or VCMRSDS = (VDxxP + VDxxN) / 2 2. VDIFFRSDS = VCLKP - VCLKN or VDIFFRSDS = VDxxP - VDxxN
10k YOUT
20k
20k
20pF VCOM=0.5VDD2
20pF
20pF
Figure 4. Yout Load Condition
17
S6C0679
PREMILINARY VER 1.0
6 BIT 420 CHANNEL RSDS TFT-LCD SOURCE DRIVER
AC CHARACTERISTICS
Table 6. AC Characteristics (Ta = - 20 to 75 C, VDD2 = 7.0 to 10.5 V, VSS1 = VSS2 = 0 V) Parameter Clock pulse width Clock pulse low period Clock pulse high period Data setup time Data hold time Start pulse setup time Start pulse hold time Start pulse delay time DIO signal pulse width CLK1 setup time CLK1 high pulse width Driver output delay time1 Driver output delay time2 Repair output delay time1 Repair output delay time2 Last data timing CLK1-CLK2 time POL-CLK1 time CLK1-POL time Symbol PWCLK PWCLK(L) PWCLK(H) tSETUP1 tHOLD1 tSETUP2 tHOLD2 tPLH1 PWDIO tSETUP3 PWCLK1 tPHL1 tPHL2 tPHL3 tPHL4 tLDT tCLK1-CLK2 tPOL-CLK1 tCLK1-POL (1) (3) (2) (3)
Condition CL = 15pF
Min. 15 6 6 2 0 4 2 1CLKP 2CLKP 0.5 1CLKP 4 14 10
Typ. -
Max. 12 2CLKP 2 6 10 6 10
Unit
ns
CLKP period
s
CL = 150pF CL = 150pF CLK1 CLKP POL or CLK1 CLK1 POL or
-
-
CLKP period ns
NOTES: 1. The value is specified when the drive voltage value reaches the target output voltage level of 90% 2. The value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy. 3. Yout load condition (refer to Figure 4. Yout Load Condition)
18
PWCLK(L) PWCLK(H)
CLKP-CLKN (RSDS)
PWCLK tLDT
WAVEFORMS
Input
tPLH1
PWDIO
DIO1; SHL=H DIO2; SHL=L
tPHL1
DxxP-DxxN (RSDS) Invalid
EVEN ODD EVEN ODD EVEN ODD EVEN ODD EVEN ODD
Invalid
Output
90% 10%
1st Data
2nd Data
DIO1; SHL=H DIO2; SHL=L
tCLK1-CLK2 PWCLK1
90% 10% 90% 10%
6 BIT 420 CHANNEL RSDS TFT-LCD SOURCE DRIVER
CLK1
tPOL-CLK1
90% 10%
tCLK1-POL
90% 10%
POL
Figure 5. Waveforms
VIHRSDS 0V VILRSDS
tPHL1 tPHL2
Y1 to Y420
90%
PREMILINARY VER 1.0
RPO1, RPO2
tPHL3
90%
tPHL4
CLKP-CLKN
CLKP-CLKN
VIHRSDS 0V VILRSDS
tHOLD1 tSETUP1
tSETUP2 tHOLD2
tSETUP1 tHOLD1
Input
90%
90%
DIO1; SHL=H DIO2; SHL=L
DxxP-DxxN
VIHRSDS 0V VILRSDS
S6C0679
19
S6C0679
PREMILINARY VER 1.0
6 BIT 420 CHANNEL RSDS TFT-LCD SOURCE DRIVER
RSDS DATA TIMING DIAGRAM
tHOLD2 tSETUP2 tSETUP1
tHOLD1 tSETUP1
tHOLD1
CLKP
Input DIO: SHL=H DOI: SHL=L
D00P/N
R[0] 1
R[1] 1
R[0] 2
R[1] 2
R[0] 3
R[1] 3
R[0] 4
R[1] 4
D01P/N
R[2] 1
R[3] 1
R[2] 2
R[3] 2
R[2] 3
R[3] 3
R[2] 4
R[3] 4
D02P/N
R[4] 1
R[5] 1
R[4] 2
R[5] 2
R[4] 3
R[5] 3
R[4] 4
R[5] 4
D10P/N
G[0] 1
G[1] 1
G[0] 2
G[1] 2
G[0] 3
G[1] 3
G[0] 4
G[1] 4
D11P/N
G[2] 1
G[3] 1
G[2] 2
G[3] 2
G[2] 3
G[3] 3
G[2] 4
G[3] 4
D12P/N
G[4] 1
G[5] 1
G[4] 2
G[5] 2
G[4] 3
G[5] 3
G[4] 4
G[5] 4
D20P/N
B[0] 1
B[1] 1
B[0] 2
B[1] 2
B[0] 3
B[1] 3
B[0] 4
B[1] 4
D21P/N
B[2] 1
B[3] 1
B[2] 2
B[3] 2
B[2] 3
B[3] 3
B[2] 4
B[3] 4
D22P/N
B[4] 1
B[5] 1
B[4] 2
B[5] 2
B[4] 3
B[5] 3
B[4] 4
B[5] 4
Figure 6. RSDS Data Timing Diagram
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